1. Field of the Invention
The present invention relates to an electrically data-rewritable non-volatile semiconductor memory device, and particularly to a non-volatile semiconductor memory device in which a physical checker pattern, a logical checker pattern or the like can be written at high speed, and a writing method therefore.
2. Description of the Related Art
Recently, non-volatile semiconductor memory devices, particularly flash memories have been broadly used in various fields because data are electrically rewritable in the flash memories and also data can be held even when power is turned off. For example, they are used as storage devices for storing data in portable terminals such as cellular phones, digital cameras, silicon audio players, etc. Furthermore, a flash memory is also used as a rewritable program storing area in a system LSI such as a microcomputer or the like.
In an inspection process of flash memories, it is needed to write a physical checker pattern corresponding to a checkered pattern, a logical checker pattern in which logical values of read-out data are inverted every adjacent bits and also the same bits are inverted every read-out cycle (for example, a pattern in which read-out data is changed like 55h→AAh→55h→AAh) or the like and check whether there is neither short-circuit between adjacent bit lines, adjacent word lines nor interference between adjacent bits.
A writing operation of a physical checker pattern in a conventional flash memory will be described hereunder with reference to the drawings. FIG. 15 is a diagram showing a memory cell array of the conventional flash memory and the construction of a writing circuit, and the same construction is disclosed by Patent Document 1 to Patent Document 5.
In FIG. 15, a memory cell array 10 is an NOR-type flash memory array. Specifically describing, the memory cell array 10 is equipped with word lines WL0 to WL3, bit lines BL0 to BL3 (there is illustrated a case where there are provided four word lines and four bit lines), and the memory cells M00 to M33 are arranged in a matrix form at the cross points of the word lines and the bit lines. The control gates of the memory cells are connected to the word lines WL0 to WL3, the drains are connected to the bit lines BL0 to BL3, the source lines are connected to a source line SL and a substrate is connected to a well line PW. Here, the sources of the memory cells M00 to M33 are connected to the common source line SL, and the substrate is connected to the common well line PW to form one erasure block. Here, an assembly of memory cells connected to the same word line is called as a page. For example, an assembly of memory cells connected to the word line WL0 is called as a page 0, and an assembly of memory cells connected to the word line WL1 is called as a page 1.
A word line driver 20 is a circuit for selecting a word line and applying a predetermined voltage. Writing circuits 1530a to 1530d are connected to the bit lines BL0 to BL3 respectively, and they comprise bit line reset transistors RT, latch circuits L0 to L3, bit line connecting circuits TG and P-channel type transistors P0 and P1. The bit line reset transistors RT are circuits for setting the bit lines to the ground voltage, and they are controlled on the basis of a control signal RS. The latch circuits L0 to L3 are circuits for temporarily storing writing data, and each of them comprises two inverter circuits. A power source of the inverter circuits is connected to a high voltage power source line VPP. Here, when 0-data (program data) is stored from data input nodes IO and/IO, the nodes NL0 to NL3 of the latch circuits are set to H level, and when 1-data (erase data) is stored, the nodes NL0 to NL3 of the latch circuits are set to L level. The bit line connecting circuits TG are circuits for connecting/disconnecting the latch circuits L0 to L3 to/from the bit lines BL0 to BL3, and they are controlled on the basis of a control signal TS.
The P-channel type transistors P0, P1 detect the bit line potential in a verifying operation and rewrite data stored in the latch circuits L0 to L3 when the threshold voltage of the memory cell reaches a predetermined value. The gates of the P-channel type transistors P0 are connected to the bit lines BL0 to BL3 respectively, and the gates of the P-channel type transistors P1 are connected to the output of an inverter INV2 controlled on the basis of a control signal VR. In the verifying operation, the control signal VR is set to H level, and the P-channel type transistors P1 are turned on. At this time, When the bit line potential is reduced to a predetermined voltage or less, the P-channel type transistors P0 are turned on, and the nodes NL0 to NL3 of the latch circuits L0 to L3 are set to L level, that is, rewritten into 1-data (erase data). Therefore, the subsequent program operation is not carried out.
N-channel type transistors N1 are used together with a verify judgment circuit 40, and detect the data stored in the latch circuits L0 to L3 to detect whether the threshold voltages of all the memory cells reach the predetermined value.
The verify judgment circuit 40 is a circuit for detecting that the writing operation of all the memory cells is completed, and controlled on the basis of a control signal NVR. The N-channel type transistors N1 of the writing circuits 1530a to 1530d and the P-channel type transistor P2 of the verify judgment circuit 40 are designed in a wired OR connection structure. During the verify operation, the NVR signal is set to L level, and when 0-data (program data) is stored in at least one bit of the latch circuits L0 to L3, that is, any one of the nodes NL0 to NL3 of the latch circuits is set to H level, some N-channel type transistor N1 is turned on and thus a PASS signal of L level is output. When all the data of the latch circuits L0 to L3 are rewritten into 1-data (erase data) by the verify operation, that is, when all the nodes NL0 to NL3 of the latch circuits are set to L level, all the N-channel type transistors N1 are turned off, and a PASS signal of H level is output. By detecting the PASS signal of H level, the completion of the writing operation can be detected.
A column gate 50 is a circuit for connecting the input data IO, /IO with the latch circuits L0 to L3 of the writing circuits 1530a to 1530d, and it is constructed by column gates YG0 to YG3, and controlled on the basis of control signals CS0 to CS3. A column driver 60 is a circuit for selecting a prescribed column gate.
FIG. 16 is a flowchart showing the writing operation of a physical checker pattern. When the program operation is started (step S1601), data latch is carried out to store writing data of page 0 into the latch circuits L0 to L3 (step S1602). Here, the pattern of the writing data is a physical checker pattern of a checkered pattern, and thus the data to be stored into the latch circuits L0 to L3 repeats each of 0-data and 1-data alternately every bit line like 0-data is stored in the latch circuit L0, 1-data is stored in the latch circuit L1, 0-data is stored in the latch circuit L2 and 1-data is stored in the latch circuit L3. After the data latch is finished, the word line WL0 is selected, the bit line connection circuit TG is set to an active state, the latch circuits L0 to L3 are connected to the bit lines BL0 to BL3 and then the program operation of the page 0 is carried out (step S1603). Accordingly, 0-data is written in the memory cells M00, M02. After the program operation of the page 0 is finished, the verify operation of the page 0 is carried out (step S1604).
When it is judged that the threshold voltage of a memory cell for which the program operation is carried out in the verify operation has reached a predetermined value, the latch data of the latch circuit corresponding to the memory cell concerned is rewritten from 0-data (program data) to 1-data (erase data), and afterwards the program operation is not carried out. On the other hand, when it is detected that the threshold voltage of the memory cell for which the program operation is carried does not reach the predetermined value, the latch data of the latch circuit corresponding to the memory cell concerned remains 0-data (program data), and subsequently the program operation is carried out (step S1605). If it is judged in step S1605 that the program operation of all the memory cells of the page is not completed, the program operation and the verify operation for the page 0 are carried out again, and the steps S1603 to S1605 are repetitively carried out until the program operation of all the memory cells of the page 0 is completed. On the other hand, if it is judged in step S1605 that the program operation of all the memory cells of the page 0 is completed, the processing goes to step S1606 to carry out the program operation of the page 1.
In the program operation of the page 1, data latch is carried out to store writing data of the page 1 into the latch circuits L0 to L3 (step S1606). Here, with respect to the data to be stored into the latch circuits L0 to L3, the inverse data to the data of the page 0 are stored like 1-data is stored in the latch circuit L0, 0-data is stored in the latch circuit L1, 1-data is stored in the latch circuit L2 and 0-data is stored in the latch circuit L3. After the data latch is finished, the word line WL1 is selected, the bit line connecting circuit TG is set to an active state to connect the latch circuits L0 to L3 to the bit lines BL0 to BL3, and the program operation of the page 1 is carried out (step S1607), whereby 0-data is written into the memory cells M11, M13. After the program operation of the page 1 is finished, the verify operation of the page 1 is carried out (step S1608), and it is judged whether the program operation of all the memory cells of the page 1 is completed (step S1609). If it is judged in step S1609 that the program operation of all the memory cells of the page 1 is completed, the processing goes to step S1610. On the other hand, it is judged in step S1609 that the writing operation of all the memory cells of the page 1 is not completed, the program operation and the verify operation of the page 1 are carried out, and the steps S1607 to S1609 are repetitively carried out until the program operation of all the memory cells of the page 1 is completed. When the program operation and the verify operation are carried out over plural cycles and the writing operation of all the memory cells of the page 1 is completed, the program operations of the page 2 and subsequent pages are subsequently carried out (step S1610).
JP-A-2002-203393, JP-A-2001-229684, JP-A-11-328981, JP-A-11-203879, JP-A-11-121721 are cited as the related art.
However, the conventional non-volatile semiconductor memory device described above has the following problems. Recently, the memory capacity of the non-volatile semiconductor memory device has been increased, and the number of pages is increased in connection with the increase of the memory capacity. Therefore, there is a tendency that the number of writing cycles will be further increased in the future. Increase of the number of writing cycles greatly affects increase of the writing time. The factors for increasing the writing time in connection with the increase of the number of cycles are (1) the data writing time of the flash memory is in micro-second order and thus it is late, and (2) a voltage generating circuit is required to generate voltages needed for the program operation and the verify operation every program operation, verify operation, and thus a voltage output stabilizing setup time is needed until the voltage generating circuit outputs a predetermined voltage and stabilized when each of the program operation and the verify operation is started. Therefore, there is a problem that the program operation and the verify operation are repetitively carried out plural cycles in the writing operation of one page, so that the writing time is increased.
Furthermore, the number of bits of one page (the number of bits to be written in a lump) is increased in connection with the increase of the memory capacity of the non-volatile semiconductor memory device, so that there is a problem that the data latch time in the writing operation of one page is increased. In some recent non-volatile semiconductor memory devices, the data latch time of one page is lengthened to the micro-second order, and thus the increase of the memory capacity greatly affects the increase of the writing time.
As described above, according to the above problems, the writing time of the physical checker pattern, the logical checker pattern in the inspection process is increased, resulting in increase of the inspection cost, that is, the chip cost, and this is not preferable.